Apparatus and methods for programming memory cells responsive to an indication of age of the memory cells

ABSTRACT

Methods of operating a memory, and memory configured to perform similar methods, may include determining a memory cell age of a plurality of memory cells, determining a desired programming step voltage for programming memory cells having the determined memory cell age, and performing a programming operation on the plurality of memory cells using the desired programming step voltage corresponding to the determined memory cell age. Methods may further include configuring a memory, including characterizing a read window budget for a programming operation of the memory as a function of a programming step voltage for a plurality of memory cell ages.

RELATED APPLICATION

This Application is a Divisional of U.S. application Ser. No.16/225,036, titled “APPARATUS AND METHODS FOR PROGRAMMING MEMORY CELLSRESPONSIVE TO AN INDICATION OF AGE OF THE MEMORY CELLS,” filed Dec. 19,2018 (Allowed) which is commonly assigned and incorporated herein byreference.

TECHNICAL FIELD

The present disclosure relates generally to memory and, in particular,in one or more embodiments, the present disclosure relates to apparatusand methods for programming memory cells responsive to an indication ofage of the memory cells.

BACKGROUND

Memories (e.g., memory devices) are typically provided as internal,semiconductor, integrated circuit devices in computers or otherelectronic devices. There are many different types of memory includingrandom-access memory (RAM), read only memory (ROM), dynamic randomaccess memory (DRAM), synchronous dynamic random access memory (SDRAM),and flash memory.

Flash memory has developed into a popular source of non-volatile memoryfor a wide range of electronic applications. Flash memory typically usea one-transistor memory cell that allows for high memory densities, highreliability, and low power consumption. Changes in threshold voltage(Vt) of the memory cells, through programming (which is often referredto as writing) of charge storage structures (e.g., floating gates orcharge traps) or other physical phenomena (e.g., phase change orpolarization), determine the data state (e.g., data value) of eachmemory cell. Common uses for flash memory and other non-volatile memoryinclude personal computers, personal digital assistants (PDAs), digitalcameras, digital media players, digital recorders, games, appliances,vehicles, wireless devices, mobile telephones, and removable memorymodules, and the uses for non-volatile memory continue to expand.

A NAND flash memory is a common type of flash memory device, so calledfor the logical form in which the basic memory cell configuration isarranged. Typically, the array of memory cells for NAND flash memory isarranged such that the control gate of each memory cell of a row of thearray is connected together to form an access line, such as a word line.Columns of the array include strings (often termed NAND strings) ofmemory cells connected together in series between a pair of selectgates, e.g., a source select transistor and a drain select transistor.Each source select transistor may be connected to a source, while eachdrain select transistor may be connected to a data line, such as columnbit line. Variations using more than one select gate between a string ofmemory cells and the source, and/or between the string of memory cellsand the data line, are known.

In programming memory, memory cells might be programmed as what areoften termed single-level cells (SLC). SLC may use a single memory cellto represent one digit (e.g., one bit) of data. For example, in SLC, aVt of 2.5V or higher might indicate a programmed memory cell (e.g.,representing a logical 0) while a Vt of −0.5V or lower might indicate anerased memory cell (e.g., representing a logical 1). Such memory mightachieve higher levels of storage capacity by including multi-level cells(MLC), triple-level cells (TLC), quad-level cells (QLC), etc., orcombinations thereof in which the memory cell has multiple levels thatenable more digits of data to be stored in each memory cell. Forexample, MLC might be configured to store two digits of data per memorycell represented by four Vt ranges, TLC might be configured to storethree digits of data per memory cell represented by eight Vt ranges, QLCmight be configured to store four digits of data per memory cellrepresented by sixteen Vt ranges, and so on.

Programming memory cells typically utilizes an iterative process ofapplying a programming pulse to a memory cell and verifying if thatmemory cell has reached its desired data state in response to thatprogramming pulse, and repeating that iterative process until thatmemory cell passes the verification. Once a memory cell passes theverification, it may be inhibited from further programming. Theiterative process can be repeated with changing (e.g., increasing)voltage levels of the programming pulse until each memory cell selectedfor the programming operation has reached its respective desired datastate, or some failure is declared, e.g., reaching a maximum number ofallowed programming pulses during the programming operation. Given theiterative nature of programming operations, and the relatively highvoltage levels each iteration uses, programming operations can besignificant influences on both the speed and power consumption of amemory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram of a memory in communication with aprocessor as part of an electronic system, according to an embodiment.

FIGS. 2A-2C are schematics of portions of an array of memory cells ascould be used in a memory of the type described with reference to FIG.1.

FIG. 3 is a conceptual depiction of threshold voltage ranges of aplurality of memory cells.

FIGS. 4A-4D are conceptual depictions of threshold voltage distributionsof a plurality of memory cells at various data ages and various memorycell ages.

FIG. 5 is a conceptual depiction of programming voltages as a functionof pulse count for various memory cell ages.

FIG. 6 is a conceptual depiction of programming voltages as a functionof pulse count for various memory cell ages in accordance with anembodiment.

FIG. 7A shows a plot of an access line voltage versus time of aprogramming operation in accordance with embodiments.

FIG. 7B shows a plot of an access line voltage versus time of aprogramming operation in accordance with other embodiments.

FIG. 8A depicts a plot of read window budget versus programming stepvoltage at various memory cell ages for use with embodiments.

FIG. 8B depicts a plot of ΔVgVt versus program/erase cycles for use withembodiments.

FIG. 9 depicts various decreasing functions for use with embodiments.

FIG. 10 is a flowchart of a method of configuring a memory in accordancewith an embodiment.

FIG. 11 is a flowchart of a method of operating a memory in accordancewith another embodiment.

FIG. 12 is a flowchart of a method of operating a memory in accordancewith a further embodiment.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings that form a part hereof, and in which is shown, byway of illustration, specific embodiments. In the drawings, likereference numerals describe substantially similar components throughoutthe several views. Other embodiments may be utilized and structural,logical and electrical changes may be made without departing from thescope of the present disclosure. The following detailed description is,therefore, not to be taken in a limiting sense.

The term “semiconductor” used herein can refer to, for example, a layerof material, a wafer, or a substrate, and includes any basesemiconductor structure. “Semiconductor” is to be understood asincluding silicon-on-sapphire (SOS) technology, silicon-on-insulator(SOI) technology, thin film transistor (TFT) technology, doped andundoped semiconductors, epitaxial layers of a silicon supported by abase semiconductor structure, as well as other semiconductor structureswell known to one skilled in the art. Furthermore, when reference ismade to a semiconductor in the following description, previous processsteps may have been utilized to form regions/junctions in the basesemiconductor structure, and the term semiconductor can include theunderlying layers containing such regions/junctions. The term conductiveas used herein, as well as its various related forms, e.g., conduct,conductively, conducting, conduction, conductivity, etc., refers toelectrically conductive unless otherwise apparent from the context.Similarly, the term connecting as used herein, as well as its variousrelated forms, e.g., connect, connected, connection, etc., refers toelectrically connecting unless otherwise apparent from the context.

FIG. 1 is a simplified block diagram of a first apparatus, in the formof a memory (e.g., memory device) 100, in communication with a secondapparatus, in the form of a processor 130, as part of a third apparatus,in the form of an electronic system, according to an embodiment. Someexamples of electronic systems include personal computers, personaldigital assistants (PDAs), digital cameras, digital media players,digital recorders, games, appliances, vehicles, wireless devices, mobiletelephones and the like. The processor 130, e.g., a controller externalto the memory device 100, may be a memory controller or other externalhost device.

Memory device 100 includes an array of memory cells 104 logicallyarranged in rows and columns. Memory cells of a logical row aretypically connected to the same access line (commonly referred to as aword line) while memory cells of a logical column are typicallyselectively connected to the same data line (commonly referred to as abit line). A single access line may be associated with more than onelogical row of memory cells and a single data line may be associatedwith more than one logical column. Memory cells (not shown in FIG. 1) ofat least a portion of array of memory cells 104 are capable of beingprogrammed to one of at least two target data states.

A row decode circuitry 108 and a column decode circuitry 110 areprovided to decode address signals. Address signals are received anddecoded to access the array of memory cells 104. Memory device 100 alsoincludes input/output (I/O) control circuitry 112 to manage input ofcommands, addresses and data to the memory device 100 as well as outputof data and status information from the memory device 100. An addressregister 114 is in communication with I/O control circuitry 112 and rowdecode circuitry 108 and column decode circuitry 110 to latch theaddress signals prior to decoding. A command register 124 is incommunication with I/O control circuitry 112 and control logic 116 tolatch incoming commands. A trim register 128 may be in communicationwith the control logic 116. The trim register 128 might represent avolatile memory, latches or other storage location, volatile ornon-volatile. For some embodiments, the trim register 128 mightrepresent a portion of the array of memory cells 104. The trim register128 might store information relating to the determination of an age ofmemory cells, the determination of programming step voltages, and/or thedetermination of programming start voltages, in accordance withembodiments. The control logic 116 might be configured to performmethods of operating a memory in accordance with embodiments.

A controller (e.g., the control logic 116 internal to the memory device100) controls access to the array of memory cells 104 in response to thecommands and generates status information for the external processor130, i.e., control logic 116 is configured to perform access operations(e.g., read operations, programming operations and/or erase operations)on the array of memory cells 104. The control logic 116 is incommunication with row decode circuitry 108 and column decode circuitry110 to control the row decode circuitry 108 and column decode circuitry110 in response to the addresses.

Control logic 116 is also in communication with a cache register 118.Cache register 118 latches data, either incoming or outgoing, asdirected by control logic 116 to temporarily store data while the arrayof memory cells 104 is busy writing or reading, respectively, otherdata. During a programming operation (e.g., write operation), data maybe passed from the cache register 118 to the data register 120 fortransfer to the array of memory cells 104; then new data may be latchedin the cache register 118 from the I/O control circuitry 112. During aread operation, data may be passed from the cache register 118 to theI/O control circuitry 112 for output to the external processor 130; thennew data may be passed from the data register 120 to the cache register118. The cache register 118 and/or the data register 120 may form (e.g.,may form a portion of) a page buffer of the memory device 100. A pagebuffer may further include sensing devices (not shown in FIG. 1) tosense a data state of a memory cell of the array of memory cells 104,e.g., by sensing a state of a data line connected to that memory cell. Astatus register 122 may be in communication with I/O control circuitry112 and control logic 116 to latch the status information for output tothe processor 130.

Memory device 100 receives control signals at control logic 116 fromprocessor 130 over a control link 132. The control signals might includea chip enable CE #, a command latch enable CLE, an address latch enableALE, a write enable WE #, a read enable RE #, and a write protect WP #.Additional or alternative control signals (not shown) may be furtherreceived over control link 132 depending upon the nature of the memorydevice 100. Memory device 100 receives command signals (which representcommands), address signals (which represent addresses), and data signals(which represent data) from processor 130 over a multiplexedinput/output (I/O) bus 134 and outputs data to processor 130 over I/Obus 134.

For example, the commands may be received over input/output (I/O) pins[7:0] of I/O bus 134 at I/O control circuitry 112 and may then bewritten into command register 124. The addresses may be received overinput/output (I/O) pins [7:0] of I/O bus 134 at I/O control circuitry112 and may then be written into address register 114. The data may bereceived over input/output (I/O) pins [7:0] for an 8-bit device orinput/output (I/O) pins [15:0] for a 16-bit device at I/O controlcircuitry 112 and then may be written into cache register 118. The datamay be subsequently written into data register 120 for programming thearray of memory cells 104. For another embodiment, cache register 118may be omitted, and the data may be written directly into data register120. Data may also be output over input/output (I/O) pins [7:0] for an8-bit device or input/output (I/O) pins [15:0] for a 16-bit device.

It will be appreciated by those skilled in the art that additionalcircuitry and signals can be provided, and that the memory device 100 ofFIG. 1 has been simplified. It should be recognized that thefunctionality of the various block components described with referenceto FIG. 1 may not necessarily be segregated to distinct components orcomponent portions of an integrated circuit device. For example, asingle component or component portion of an integrated circuit devicecould be adapted to perform the functionality of more than one blockcomponent of FIG. 1. Alternatively, one or more components or componentportions of an integrated circuit device could be combined to performthe functionality of a single block component of FIG. 1.

Additionally, while specific I/O pins are described in accordance withpopular conventions for receipt and output of the various signals, it isnoted that other combinations or numbers of I/O pins (or other I/O nodestructures) may be used in the various embodiments.

FIG. 2A is a schematic of a portion of an array of memory cells 200A,such as a NAND memory array, as could be used in a memory of the typedescribed with reference to FIG. 1, e.g., as a portion of array ofmemory cells 104. Memory array 200A includes access lines, such as wordlines 202 ₀ to 202 _(N), and data lines, such as bit lines 204 ₀ to 204_(M). The word lines 202 may be connected to global access lines (e.g.,global word lines), not shown in FIG. 2A, in a many-to-one relationship.For some embodiments, memory array 200A may be formed over asemiconductor that, for example, may be conductively doped to have aconductivity type, such as a p-type conductivity, e.g., to form ap-well, or an n-type conductivity, e.g., to form an n-well.

Memory array 200A might be arranged in rows (each corresponding to aword line 202) and columns (each corresponding to a bit line 204). Eachcolumn may include a string of series-connected memory cells (e.g.,non-volatile memory cells), such as one of NAND strings 206 ₀ to 206_(M). Each NAND string 206 might be connected (e.g., selectivelyconnected) to a common source (SRC) 216 and might include memory cells208 ₀ to 208 _(N). The memory cells 208 may represent non-volatilememory cells for storage of data. The memory cells 208 of each NANDstring 206 might be connected in series between a select gate 210 (e.g.,a field-effect transistor), such as one of the select gates 210 ₀ to 210_(M) (e.g., that may be source select transistors, commonly referred toas select gate source), and a select gate 212 (e.g., a field-effecttransistor), such as one of the select gates 212 ₀ to 212 _(M) (e.g.,that may be drain select transistors, commonly referred to as selectgate drain). Select gates 210 ₀ to 210 _(M) might be commonly connectedto a select line 214, such as a source select line (SGS), and selectgates 212 ₀ to 212 _(M) might be commonly connected to a select line215, such as a drain select line (SGD). Although depicted as traditionalfield-effect transistors, the select gates 210 and 212 may utilize astructure similar to (e.g., the same as) the memory cells 208. Theselect gates 210 and 212 might represent a plurality of select gatesconnected in series, with each select gate in series configured toreceive a same or independent control signal.

A source of each select gate 210 might be connected to common source216. The drain of each select gate 210 might be connected to a memorycell 208 ₀ of the corresponding NAND string 206. For example, the drainof select gate 210 ₀ might be connected to memory cell 208 ₀ of thecorresponding NAND string 206 ₀. Therefore, each select gate 210 mightbe configured to selectively connect a corresponding NAND string 206 tocommon source 216. A control gate of each select gate 210 might beconnected to select line 214.

The drain of each select gate 212 might be connected to the bit line 204for the corresponding NAND string 206. For example, the drain of selectgate 212 ₀ might be connected to the bit line 204 ₀ for thecorresponding NAND string 206 ₀. The source of each select gate 212might be connected to a memory cell 208 _(N) of the corresponding NANDstring 206. For example, the source of select gate 212 ₀ might beconnected to memory cell 208 _(N) of the corresponding NAND string 206₀. Therefore, each select gate 212 might be configured to selectivelyconnect a corresponding NAND string 206 to the corresponding bit line204. A control gate of each select gate 212 might be connected to selectline 215.

The memory array in FIG. 2A might be a quasi-two-dimensional memoryarray and might have a generally planar structure, e.g., where thecommon source 216, NAND strings 206 and bit lines 204 extend insubstantially parallel planes. Alternatively, the memory array in FIG.2A might be a three-dimensional memory array, e.g., where NAND strings206 may extend substantially perpendicular to a plane containing thecommon source 216 and to a plane containing the bit lines 204 that maybe substantially parallel to the plane containing the common source 216.

Typical construction of memory cells 208 includes a data-storagestructure 234 (e.g., a floating gate, charge trap, or other structureconfigured to store charge) that can determine a data state of thememory cell (e.g., through changes in threshold voltage), and a controlgate 236, as shown in FIG. 2A. The data-storage structure 234 mayinclude both conductive and dielectric structures while the control gate236 is generally formed of one or more conductive materials. In somecases, memory cells 208 may further have a defined source/drain (e.g.,source) 230 and a defined source/drain (e.g., drain) 232. Memory cells208 have their control gates 236 connected to (and in some cases form) aword line 202.

A column of the memory cells 208 may be a NAND string 206 or a pluralityof NAND strings 206 selectively connected to a given bit line 204. A rowof the memory cells 208 may be memory cells 208 commonly connected to agiven word line 202. A row of memory cells 208 can, but need not,include all memory cells 208 commonly connected to a given word line202. Rows of memory cells 208 may often be divided into one or moregroups of physical pages of memory cells 208, and physical pages ofmemory cells 208 often include every other memory cell 208 commonlyconnected to a given word line 202. For example, memory cells 208commonly connected to word line 202 _(N) and selectively connected toeven bit lines 204 (e.g., bit lines 204 ₀, 204 ₂, 204 ₄, etc.) may beone physical page of memory cells 208 (e.g., even memory cells) whilememory cells 208 commonly connected to word line 202 _(N) andselectively connected to odd bit lines 204 (e.g., bit lines 204 ₁, 204₃, 204 ₅, etc.) may be another physical page of memory cells 208 (e.g.,odd memory cells). Although bit lines 204 ₃-204 ₅ are not explicitlydepicted in FIG. 2A, it is apparent from the figure that the bit lines204 of the array of memory cells 200A may be numbered consecutively frombit line 204 ₀ to bit line 204 _(M). Other groupings of memory cells 208commonly connected to a given word line 202 may also define a physicalpage of memory cells 208. For certain memory devices, all memory cellscommonly connected to a given word line might be deemed a physical pageof memory cells. The portion of a physical page of memory cells (which,in some embodiments, could still be the entire row) that is read duringa single read operation or programmed during a single programmingoperation (e.g., an upper or lower page of memory cells) might be deemeda logical page of memory cells. A block of memory cells may includethose memory cells that are configured to be erased together, such asall memory cells connected to word lines 202 ₀-202 _(N) (e.g., all NANDstrings 206 sharing common word lines 202). Unless expresslydistinguished, a reference to a page of memory cells herein refers tothe memory cells of a logical page of memory cells.

Although the example of FIG. 2A is discussed in conjunction with NANDflash, the embodiments and concepts described herein are not limited toa particular array architecture or structure, and can include otherstructures (e.g., SONOS or other data storage structure configured tostore charge) and other architectures (e.g., AND arrays, NOR arrays,etc.).

FIG. 2B is another schematic of a portion of an array of memory cells200B as could be used in a memory of the type described with referenceto FIG. 1, e.g., as a portion of array of memory cells 104. Likenumbered elements in FIG. 2B correspond to the description as providedwith respect to FIG. 2A. FIG. 2B provides additional detail of oneexample of a three-dimensional NAND memory array structure. Thethree-dimensional NAND memory array 200B may incorporate verticalstructures which may include semiconductor pillars where a portion of apillar may act as a channel region of the memory cells of NAND strings206. The NAND strings 206 may be each selectively connected to a bitline 204 ₀-204 _(M) by a select transistor 212 (e.g., that may be drainselect transistors, commonly referred to as select gate drain) and to acommon source 216 by a select transistor 210 (e.g., that may be sourceselect transistors, commonly referred to as select gate source).Multiple NAND strings 206 might be selectively connected to the same bitline 204. Subsets of NAND strings 206 can be connected to theirrespective bit lines 204 by biasing the select lines 215 ₀-215 _(K) toselectively activate particular select transistors 212 each between aNAND string 206 and a bit line 204. The select transistors 210 can beactivated by biasing the select line 214. Each word line 202 may beconnected to multiple rows of memory cells of the memory array 200B.Rows of memory cells that are commonly connected to each other by aparticular word line 202 may collectively be referred to as tiers.

FIG. 2C is a further schematic of a portion of an array of memory cells200C as could be used in a memory of the type described with referenceto FIG. 1, e.g., as a portion of array of memory cells 104. Likenumbered elements in FIG. 2C correspond to the description as providedwith respect to FIG. 2A. Array of memory cells 200C may include stringsof series-connected memory cells (e.g., NAND strings) 206, access (e.g.,word) lines 202, data (e.g., bit) lines 204, select lines 214 (e.g.,source select lines), select lines 215 (e.g., drain select lines) andsource 216 as depicted in FIG. 2A. A portion of the array of memorycells 200A may be a portion of the array of memory cells 200C, forexample. FIG. 2C depicts groupings of NAND strings 206 into blocks ofmemory cells 250. Blocks of memory cells 250 may be groupings of memorycells 208 that may be erased together in a single erase operation,sometimes referred to as erase blocks. Each block of memory cells 250might represent those NAND strings 206 commonly associated with a singleselect line 215, e.g., select line 215 ₀. The source 216 for the blockof memory cells 2500 might be a same source as the source 216 for theblock of memory cells 250 _(L). For example, each block of memory cells250 ₀-250 _(L) might be commonly selectively connected to the source216. Access lines 202 and select lines 214 and 215 of one block ofmemory cells 250 may have no direct connection to access lines 202 andselect lines 214 and 215, respectively, of any other block of memorycells of the blocks of memory cells 250 ₀-250 _(L).

The data lines 204 ₀-204 _(M) may be connected (e.g., selectivelyconnected) to a buffer portion 240, which might be a portion of a pagebuffer of the memory. The buffer portion 240 might correspond to amemory plane (e.g., the set of blocks of memory cells 250 ₀-250 _(L)).The buffer portion 240 might include sensing devices (not shown) forsensing data values indicated on respective data lines 204, andcorresponding registers (not shown) for storage of the sensed datavalues from its corresponding memory plane.

FIG. 3 is a conceptual depiction of threshold voltage ranges of aplurality of memory cells. FIG. 3 illustrates an example of thresholdvoltage ranges and their distributions for a population of asixteen-level memory cells, often referred to as QLC memory cells. Forexample, such a memory cell might be programmed to a threshold voltage(Vt) that falls within one of sixteen different threshold voltage ranges330 ₀-330 ₁₅, each being used to represent a data state corresponding toa bit pattern of four bits. The threshold voltage range 330 ₀ typicallyhas a greater width than the remaining threshold voltage ranges 330₁-330 ₁₅ as memory cells are generally all placed in the data statecorresponding to the threshold voltage range 330 ₀, then subsets ofthose memory cells are subsequently programmed to have thresholdvoltages in one of the threshold voltage ranges 330 ₁-330 ₁₅. Asprogramming operations are generally more incrementally controlled thanerase operations, these threshold voltage ranges 330 ₁-330 ₁₅ may tendto have tighter distributions.

The threshold voltage ranges 330 ₀, 330 ₁, 330 ₂, 330 ₃, 330 ₄, 330 ₅,330 ₆, 330 ₇, 330 ₈, 330 ₉, 330 ₁₀, 330 ₁₁, 330 ₁₂, 330 ₁₃, 330 ₁₄and330 ₁₅ might each represent a respective data state, e.g., L0, L1, L2,L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14 and L15,respectively. As an example, if the threshold voltage of a memory cellis within the first of the sixteen threshold voltage ranges 330 ₀, thememory cell in this case may be storing a data state L0 having a datavalue of logical ‘1111’ and is typically referred to as the erased stateof the memory cell. If the threshold voltage is within the second of thesixteen threshold voltage ranges 330 ₁, the memory cell in this case maybe storing a data state L1 having a data value of logical ‘0111’. If thethreshold voltage is within the third of the sixteen threshold voltageranges 330 ₂, the memory cell in this case may be storing a data stateL2 having a data value of logical ‘0011’, and so on. Table 1 providesone possible correspondence between the data states and theircorresponding logical data values. Other assignments of data states tological data values are known. Memory cells remaining in the lowest datastate (e.g., the erased state or L0 data state), as used herein, will bedeemed to be programmed to the lowest data state. The information ofTable 1 might be contained within the trim register 128, for example.

TABLE 1 Data State Logical Data Value L0 1111 L1 0111 L2 0011 L3 1011 L41001 L5 0001 L6 0101 L7 1101 L8 1100 L9 0100 L10 0000 L11 1000 L12 1010L13 0010 L14 0110 L15 1110

Following programming, threshold voltages of memory cells may shift dueto such phenomena as quick charge loss (QCL). QCL is a de-trapping ofelectrons near a gate dielectric interface out to the channel region ofthe memory cell, and can cause a Vt shift shortly after a programmingpulse. When a memory cell passes the verify operation, the programmedthreshold voltage may appear to be higher due to the trapped charge inthe gate dielectric. When the memory cell is read after the programoperation has been completed, the memory cell may have a Vt that islower than the Vt obtained during the program verify operation due tothe charge in the gate dielectric leaking out to the channel region.Threshold voltages of memory cells may further shift due to cumulativecharge loss over the age of their programmed data, e.g., a period oftime between programming the data and reading the data, referred toherein as data age. Data age is often indicated in terms of time decadessubsequent to programming. Time decades are typically defined such thatX time decades equals 10^(X) seconds, e.g., 0 time decades equals 1second, 1 time decade equals 10 seconds, 2 time decades equals 100seconds, etc. Memory cell age, as opposed to data age, is oftenindicated in terms of a number of program/erase cycles the memory cellshave experienced.

FIGS. 4A-4D are conceptual depictions of threshold voltage distributionsof a plurality of memory cells following a programming operation. Thethreshold voltage distributions 430 _(d)-430 _(d+2) of FIG. 4A mightrepresent some portion of the distributions for threshold voltage ranges330 ₀-330 ₁₅ of FIG. 3 at the completion of a programming operation formemory cells having a particular memory cell age, e.g., memory cellshaving experienced a particular number of program/erase cycles, whilethreshold voltage distributions 434 _(d)-434 _(d+2) of FIG. 4B mightrepresent the same portion of the distributions for threshold voltageranges 330 ₀-330 ₁₅ of FIG. 3 at the completion of a programmingoperation for memory cells having a different memory cell age, e.g.,memory cells having experienced a different number of program/erasecycles, greater than the particular number of program/erase cycles. Bothof the programming operations might utilize a same programming step sizebetween adjacent programming pulses.

With reference to FIG. 4A, adjacent threshold voltage distributions 430are typically separated by some margin (e.g., dead space) 432 at thecompletion of programming. For example, the threshold voltagedistribution 430 _(d) might be separated from a next lower thresholdvoltage distribution (not shown in FIG. 4A) by margin 432 _(d), andseparated from a next higher threshold voltage distribution, e.g.,threshold voltage distribution 430 _(d+1), by margin 431 _(d+1).Similarly, the threshold voltage distribution 430 _(d+1) might beseparated from a next higher threshold voltage distribution, e.g.,threshold voltage distribution 430 _(d+2), by margin 431 _(d+2), thethreshold voltage distribution 430 _(d+2) might be separated from a nexthigher threshold voltage distribution (not shown in FIG. 4A) by margin4311+3, and so on. The sum of the margins 432 for each of the thresholdvoltage distributions 430 might be referred to as a read window budget(RWB).

With reference to FIG. 4B, adjacent threshold voltage distributions 434are typically separated by some margin (e.g., dead space) 436 at thecompletion of programming. For example, the threshold voltagedistribution 434 _(d) might be separated from a next lower thresholdvoltage distribution (not shown in FIG. 4B) by margin 436 _(d), andseparated from a next higher threshold voltage distribution, e.g.,threshold voltage distribution 434 _(d+1), by margin 436 _(d+1).Similarly, the threshold voltage distribution 434 _(d+1) might beseparated from a next higher threshold voltage distribution, e.g.,threshold voltage distribution 434 _(d+2), by margin 436 _(d+2), thethreshold voltage distribution 434 _(d+2) might be separated from a nexthigher threshold voltage distribution (not shown in FIG. 4B) by margin436 _(d+3), and so on. The sum of the margins 436 for each of thethreshold voltage distributions 434 might similarly be referred to as aread window budget (RWB).

For programming operations utilizing an iterative process of applyingincreasing programming pulses to an access line (e.g., connected tocontrol gates of the memory cells), the RWB is generally highlydependent upon the programming step size, e.g., the voltage differencebetween adjacent programming pulses. However, the RWB is furtherdependent upon the age of the memory cells as memory cells experiencinghigher numbers of program/erase cycles often generally exhibit higherdegrees of coupling between adjacent charge storage structures (e.g.,floating-gate structures) and higher degrees of quick charge loss. Assuch, even where the memory cells having the particular memory cell ageof FIG. 4A and the memory cells having the different memory cell age ofFIG. 4B are programmed utilizing the same programming step size, theirRWBs might be different. Accordingly, the sum of the margins 436 of FIG.4B might be less than the sum of the margins 432 of FIG. 4A.

As previously noted, memory cells also generally experiencetime-dependent charge loss subsequent to programming. This is depictedin FIGS. 4C and 4D for the memory cells of lesser and greater memorycell ages, respectively. The threshold voltage distributions 430_(d)-430 _(d+2) of FIG. 4C might represent the threshold voltage shiftsof the threshold voltage distributions 430 _(d)-430 _(d+2) of FIG. 4A ata particular data age (e.g., a particular number of time decadessubsequent to programming), and the threshold voltage distributions 434_(d)-434 _(d+2) of FIG. 4D might represent the threshold voltage shiftsof the threshold voltage distributions 434 _(d)-434 _(d+2) of FIG. 4B atthe particular data age. Although time-dependent charge loss isgenerally dependent upon data age, because the threshold voltagedistributions 430 _(d)-430 _(d+2) of FIG. 4A exhibited a greater RWB andthe threshold voltage distributions 434 _(d)-434 _(d+2) of FIG. 4B, thethreshold voltage distributions 430 _(d)-430 _(d+2) of FIG. 4C alsoexhibit a lesser degree of overlap than the threshold voltagedistributions 434 _(d)-434 _(d+2) of FIG. 4D.

With reference to FIG. 4C, a read voltage 438′_(d) might be applied tothe control gates of the plurality of memory cells during a readoperation. When read voltages are applied in increasing order during theread operation, memory cells first activating in response to the readvoltage 438′_(d) might be determined to have the data statecorresponding to the threshold voltage distribution 430 _(d). Readoperations are well understood in the art and will not be furtherdetailed herein. Due to the overlap of the threshold voltagedistributions 430 _(d) and 430 _(d+1) in FIG. 4C, resulting from thethreshold voltage shifts, some memory cells of the threshold voltagedistribution 430 _(d) will be incorrectly identified as belonging to adata state other than the data state corresponding to the thresholdvoltage distribution 430 _(d), and some memory cells of the thresholdvoltage distribution 430 _(d+1) will be incorrectly identified asbelonging to the data state corresponding to the threshold voltagedistribution 430 _(d).

With reference to FIG. 4D, a read voltage 438″_(d) might be applied tothe control gates of the plurality of memory cells during a readoperation. When read voltages are applied in increasing order during theread operation, memory cells first activating in response to the readvoltage 438″_(d) might be determined to have the data statecorresponding to the threshold voltage distribution 434 _(d). Due to theoverlap of the threshold voltage distributions 434 _(d) and 434 _(d+1)in FIG. 4D, resulting from the threshold voltage shifts, some memorycells of the threshold voltage distribution 434 _(d) will be erroneouslydetermined to belong to a data state other than the data statecorresponding to the threshold voltage distribution 434 _(d), and somememory cells of the threshold voltage distribution 434 _(d+1) will beerroneously determined to belong to the data state corresponding to thethreshold voltage distribution 434 _(d). However, as the overlap of thethreshold voltage distributions 434 _(d) and 434 _(d+1) in FIG. 4D islarger than the overlap of the threshold voltage distributions 430 _(d)and 430 _(d+1) in FIG. 4C, a larger number of memory cells would beerroneously determined to correspond to a data state different thantheir intended data state. It is noted that due to the different degreesof threshold voltage shifts between the memory cells of FIG. 4C and thememory cells of FIG. 4D, the read voltage 438″_(d) might be lower thanthe 438′_(d).

Error correction schemes are commonly used to identify and correcterroneous digits of data. However, error correction schemes havelimitations on the number of errors they are capable of identifying andcorrecting. Some known error correction schemes might utilize errorcorrection code (ECC) data conforming to Hamming codes,horizontal/vertical parity codes, convolution codes, RecursiveSystematic Codes (RSC), Trellis-Coded Modulation (TCM), Block CodedModulation (BCM), Bose-Chaudhuri-Hocquenghem (BCH) codes, Reed-Solomoncodes, turbo codes, cyclic redundancy codes (CRC) or low density paritycheck (LDPC) codes, although this disclosure is not limited to aparticular error correction scheme or its coding. The number ofcorrectable errors generally can be increased through the use of largeramounts of error correction code data, or through the use of more robusterror correction schemes, but these generally require more storage spaceand more computation time, respectively, to effect the corrections.Regardless of the number of correctable errors, the programming stepsize for an iterative programming operation has typically beendetermined to allow the selected error correction scheme to correct allexpected errors for a selected level of data retention, e.g., desiredmaximum data age, of the memory cells at their expected end of life,e.g., a desired maximum memory cell age. Error correction of data errorsis well understood in the art and will not be detailed herein.

FIG. 5 is a conceptual depiction of programming voltages as a functionof pulse count for various memory cell ages. Line 540 ₀ might representa plot of the voltage levels of a plurality of programming pulses usedto program a plurality of memory cells at a first memory cell age. Line540 ₁ might represent a plot of the voltage levels of a plurality ofprogramming pulses used to program a plurality of memory cells at asecond memory cell age greater than the first memory cell age. Line 540₂ might represent a plot of the voltage levels of a plurality ofprogramming pulses used to program a plurality of memory cells at athird memory cell age greater than the second memory cell age. Asdepicted, the programming voltages (Vpgm) generally decrease as thememory cells age, as a memory cell that has been through no or very fewprogram/erase cycles will typically require application of a highervoltage at its control gate to raise its threshold voltage by aparticular amount as compared to a memory cell that has been through ahigher number of cycles. In addition, the slopes of each of the lines540 are generally expected to satisfy the condition thaty₀/x₀=y₁/x₁=y₂/x₂.

Programming a plurality of memory cells at the first memory cell age,the second memory cell age and the third memory cell age utilizing theprogramming voltages of lines 540 ₀, 540 ₁ and 540 ₂, respectively,might be expected to produce threshold voltage distributions withdecreasing magnitudes of RWB. The RWB for the memory cells having thethird memory cell age might be an RWB that is sufficient to facilitateerror correction for those memory cells following the expected thresholdvoltage shifts, such as described with reference to FIG. 4D. Errorcorrection would also be facilitated for lesser memory cell ages, e.g.,the first memory cell age and the second memory cell age.

While selecting a programming step size to facilitate error correctionof memory cells having higher memory cell ages, e.g., the third memorycell age, might also facilitate error correction for lesser memory cellages, e.g., the first memory cell age and the second memory cell age,the error correction capabilities might be underutilized. For variousembodiments, improvements in programming time (e.g., and possibleaccompanying improvements in power consumption) might be facilitated bytargeting an RWB that might be near the limits of the selected errorcorrection scheme for a variety of memory cell ages. Programming timemight be inversely proportional (e.g., directly inversely proportional)to the slope of the programming voltages utilized for programming memorycells.

FIG. 6 is a conceptual depiction of programming voltages as a functionof pulse count for various memory cell ages in accordance with anembodiment. Line 640 ₀ might represent a plot of the voltage levels of aplurality of programming pulses used to program a plurality of memorycells at a first memory cell age, e.g., some particular number ofprogram/erase cycles. Line 640 ₁ might represent a plot of the voltagelevels of a plurality of programming pulses used to program a pluralityof memory cells at a second memory cell age greater than (e.g., agreater number of program/erase cycles than) the first memory cell age.Line 640 ₂ might represent a plot of the voltage levels of a pluralityof programming pulses used to program a plurality of memory cells at athird memory cell age greater than (e.g., a greater number ofprogram/erase cycles than) the second memory cell age. As depicted, theprogramming voltages (Vpgm) generally decrease as the memory cells age,as a memory cell that has been through no or very few program/erasecycles will typically require application of a higher voltage at itscontrol gate to raise its threshold voltage by a particular amount ascompared to a memory cell that has been through a higher number ofcycles. In addition, the slopes of the lines 640 generally decrease asthe memory cells age. For example, the slopes of each of the lines 640might be expected to satisfy the condition that y₀/x₀>y₁/x₁>y₂/x₂. Forsome embodiments, programming operations at two different memory cellages might utilize the same slopes for their programming voltages. Forexample, programming a memory cell having a memory cell agecorresponding to Z program/erase cycles might utilize a same slope forits programming voltages as programming a memory cell having a memorycell age corresponding to Z+1 program/erase cycles.

Programming a plurality of memory cells at the first memory cell age,the second memory cell age and the third memory cell age utilizing theprogramming voltages of lines 640 ₀, 640 ₁ and 640 ₂, respectively,might be expected to produce threshold voltage distributions withmagnitudes of RWB that might be within a narrower range of values (e.g.,near constant) than the magnitudes of RWB produced using constant slopesfor programming voltages at each memory cell age. The RWBs for thememory cells having the first memory cell age, the second memory cellage, and the third memory cell age might each be RWBs that aresufficient to facilitate error correction for those memory cellsfollowing the expected threshold voltage shifts.

FIG. 7A shows a plot of an access line voltage versus time of aprogramming operation in accordance with embodiments. While theprogramming voltages were depicted in FIG. 6 to be linear, programmingvoltages are often applied to an access line as a series of programmingpulses of increasing voltage level, each followed by a verify pulse.Depicted in FIG. 7A is a series of programming pulses 750 (e.g.,programming pulses 750 ₀-750 ₆), which might each be followed by averify pulse 752 (e.g., verify pulses 752 ₀-752 ₆). Note that forembodiments storing more than one digit per memory cell, there may bemore than one verify pulse 752, each with a different voltage level, todistinguish between more than two possible data states of theprogramming operation. In general, there might be one to N−1 verifypulses 752 following a programming pulse 750, where N equals a number ofpossible data states to be programmed to a plurality of memory cellsduring a programming operation. Similarly, for some embodiments, aprogramming pulse 750 might be followed by a subsequent programmingpulse 750 without any intervening verify pulses 752. For example, theverify pulse 752 ₀ might be eliminated if the programming pulse 750 ₀ isnot expected to result in any memory cell of the programming operationreaching a threshold voltage range corresponding to any data state otherthan the L0 data state. Although seven programming pulses 750 aredepicted in FIG. 7A, typical programming operations might utilizedifferent numbers (e.g., greater numbers) of programming pulses 750.

In FIG. 7A, the programming pulses 750 are depicted to have aprogramming start voltage, e.g., of an initial programming pulse 750 ₀,having a voltage level 754. Each subsequent programming pulse might behigher than its immediately prior programming pulse 750 by a voltagedifference (ΔV) 756. The slope of the programming pulses 750 might berepresented by the line 758, and might be deemed to have a slope equalto the voltage difference 756 (e.g., ΔV per one programming pulse). Thevoltage difference 756 might be determined in response to a memory cellage of the memory cells undergoing the programming operation. It isrecognized herein that even where values may be intended to be equal,variabilities and accuracies of industrial processing and operation maylead to differences from their intended values. These variabilities andaccuracies will generally be dependent upon the technology utilized infabrication and operation of the integrated circuit device. As such, ifvalues are intended to be equal, those values are deemed to be equalregardless of their resulting values.

FIG. 7B shows a plot of an access line voltage versus time of aprogramming operation in accordance with other embodiments. While theprogramming voltages were depicted in FIG. 7A to have a constant slope,programming operations might use a first slope during one portion (e.g.,an initial portion) of the programming operation, and might use a secondslope during a different portion (e.g., a remaining portion) of theprogramming operation. Such programming operations might be thought ofas using coarse and fine programming. For example, during the portion ofthe programming operation using the first slope of the programmingvoltages, the verify pulse (or verify pulses) might have a first voltagelevel (or first set of voltage levels) to determine when the memorycells are approaching their respective desired data states. When somecriteria is met, e.g., when a particular number (e.g., one or more) ofthe memory cells of the programming operation are verified at the firstvoltage level(s), the slope of the programming voltages might be changed(e.g., reduced) for a remainder of the programming operation.

Depicted in FIG. 7B is a series of programming pulses 750 (e.g.,programming pulses 750 ₀-750 ₆), which might each be followed by averify pulse 752 (e.g., verify pulses 752 ₀-752 ₆). Note that forembodiments storing more than one digit per memory cell, there may bemore than one verify pulse 752, each with a different voltage level, todistinguish between more than two possible data states of theprogramming operation. In general, there might be one to N−1 verifypulses 752 following a programming pulse 750, where N equals a number ofpossible data states to be programmed to a plurality of memory cellsduring a programming operation. Similarly, for some embodiments, aprogramming pulse 750 might be followed by a subsequent programmingpulse 750 without any intervening verify pulses 752. For example, theverify pulse 752 ₀ might be eliminated if the programming pulse 750 ₀ isnot expected to result in any memory cell of the programming operationreaching a threshold voltage range corresponding to any data state otherthan the L0 data state. Although seven programming pulses 750 aredepicted in FIG. 7B, typical programming operations might utilizedifferent numbers (e.g., greater numbers) of programming pulses 750.

In FIG. 7B, the programming pulses 750 are depicted to have aprogramming start voltage, e.g., of an initial programming pulse 750 ₀,having a voltage level 754. Each subsequent programming pulse for aparticular portion (e.g., initial portion) of the programming operationmight be higher than its immediately prior programming pulse 750 by avoltage difference (ΔV) 756. The slope of the programming pulses 750 ofthe particular portion of the programming operation might be representedby the line 758, and might be deemed to have a slope equal to thevoltage difference 756 (e.g., ΔV per one programming pulse). Using theassumption that the criteria was satisfied following the programmingpulse 750 ₃ and its verification, each subsequent programming pulse fora different portion (e.g., remaining portion) of the programmingoperation might be higher than its immediately prior programming pulse750 by a voltage difference (ΔV) 757. The slope of the programmingpulses 750 of the different portion of the programming operation mightbe represented by the line 759, and might be deemed to have a slopeequal to the voltage difference 757 (e.g., ΔV per one programmingpulse). The voltage difference 757 might be different than (e.g., lessthan) the voltage difference 756. At least one of the voltage difference757 and the voltage difference 756 might be determined in response to amemory cell age of the memory cells undergoing the programmingoperation.

FIG. 8A depicts a plot of read window budget versus programming stepvoltage at various memory cell ages for use with embodiments. As noted,various embodiments might select a programming step size for aparticular memory cell age expected to produce an RWB that is within,but near, the capabilities of a selected error correction scheme. Forvarious embodiments, this might include characterizing the performanceof a memory at various memory cell ages. The performance characteristicsof the memory, e.g., RWB as a function of programming step voltage,might, for example, be determined experimentally, empirically or throughsimulation.

In FIG. 8A, line 860 ₀ might represent the plot of memory cells of afirst memory cell age, e.g., having experienced a first number of (e.g.,zero or very few) program/erase cycles, line 860 ₁ might represent theplot of memory cells of a second memory cell age, e.g., havingexperienced a second number of program/erase cycles greater than thefirst number, line 860 ₂ might represent the plot of memory cells of athird memory cell age, e.g., having experienced a third number ofprogram/erase cycles greater than the second number, and line 860 ₃might represent the plot of memory cells of a fourth memory cell age,e.g., having experienced a fourth number of program/erase cycles greaterthan the third number. By selecting a desired RWB represented by line862, a desired programming step voltage for each of the memory cell agesmight be determined from the intersection of the line 862 with therelevant line 860.

Data for a plot of the type depicted in FIG. 8A might be determined byprogramming (e.g., simulating programming) of different pluralities ofmemory cells having a particular memory cell age using a number ofrespective programming step voltages, and then reading (e.g., simulatingreading) the programmed memory cells to determine the resulting RWB foreach of those programming step voltages to generate the data for one ofthe lines 860. This process could be repeated for different memory cellages.

FIG. 8B depicts a plot of ΔVgVt versus program/erase cycles for use withembodiments. As noted, a memory cell that has been through no or veryfew program/erase cycles will typically require application of a highervoltage at its control gate to raise its threshold voltage by aparticular amount as compared to a memory cell that has been through ahigher number of cycles. This is generally indicated as VgVt, arelationship between an applied voltage level (e.g., a gate voltage Vg)across a memory cell to its resulting threshold voltage as an indicationof a programming voltage sufficient to program a memory cell, or groupof memory cells, to a particular threshold voltage, or range ofthreshold voltages. For example, if a voltage level of 13 volts isapplied to a control gate of a memory cell whose body (e.g., channel) isat a ground potential (e.g., 0 volts), and the resulting thresholdvoltage is −0.5 volt, the VgVt for that memory cell is (13 volts−0volts)−(−0.5 volts)=13.5 volts. Various embodiments might thus includecharacterizing the performance of a memory at various memory cell ages.The performance characteristics of the memory, e.g., the difference inVgVt (ΔVgVt) from some baseline value as a function of a number ofprogram/erase cycles, might, for example, be determined experimentally,empirically or through simulation.

In FIG. 8B, line 864 might represent the plot of ΔVgVt as a function ofa number of program/erase cycles. Thus, for a particular memory cell age(e.g., a particular number of program erase cycles), a programming startvoltage might be determined by adding the ΔVgVt for that memory cell ageto a baseline programming start voltage, e.g., a programming startvoltage selected for a programming operation for memory cells havingexperienced zero program/erase cycles.

Data for a plot of the type depicted in FIG. 8B might be determined byapplying a programming pulse (e.g., simulating applying a programmingpulse) to control gates of a plurality of memory cells having differentrespective memory cell ages (e.g., program/erase cycles), and thenreading (e.g., simulating reading) the programmed memory cells todetermine the resulting VgVt to generate the data for the line 864.

FIG. 9 depicts various examples of decreasing functions of memory cellage for use with embodiments. Decreasing functions of the type depictedin FIG. 9 might generally represent functions as might be used todetermine programming step voltages and programming start voltages inaccordance with embodiments. The abscissa and ordinate mightindependently utilize a linear, logarithmic or other scale, for example.Line 972 represents a linear decreasing function, e.g., having aconstant negative slope. Line 974 represents a decreasing function ofdecreasing slope. For example, the function of line 974 may have a slopenear zero at the lower range of memory cell age, and the slope of line974 may decrease (e.g., become more negative) as the age is increased.Line 976 represents a decreasing function of increasing slope. Forexample, the function of line 976 may have a negative slope at the lowerrange of memory cell age, and the slope of line 976 may increase (e.g.,become less negative) as the age is increased. Line 978 represents astepped decreasing function having successively lower steps as thememory cell age is increased. Note that while steps of line 978 aredepicted to have equal height 977 and equal length 979, these valuescould be varied. For example, a particular step may have a greaterheight 977 and lesser length 979 than a preceding step, or it may have alesser height 977 and greater length 979 than a preceding step. Steppedfunctions may represent the use of a look-up table, where the value ofthe attribute (e.g., programming step or start voltage) is determined bylooking up the value of the memory cell age (e.g., number of experiencedprogram/erase cycles) in the table and selecting the value of theattribute corresponding to that age. Table 2 is a conceptual example ofa look-up table. Look-up tables might be stored to the memory (e.g., toa trim register 128) to allow a controller (e.g., the control logic 116)to select the attribute in response to an indication of memory cell age.Alternatively, the value of the attribute for a decreasing function maybe directly calculated from an equation of the decreasing function,e.g., Y=f(A), and constants of the equation might be stored to thememory (e.g., to a trim register 128) to allow a controller (e.g., thecontrol logic 116) to calculate the attribute in response to anindication of memory cell age.

TABLE 2 Attribute Values (Y) as Function of Memory Cell Age (A) MemoryCell Age (A) Attribute Value (Y) A1 <= A < A2 Y1 A2 <= A < A3 Y2 A3 <= A< A4 Y3 A4 <= A <= A5 Y4

While several examples of decreasing functions are described withreference to FIG. 9, other decreasing functions can be used where avalue of the attribute at some relevant memory cell age is less than orequal to the value of the attribute (e.g., programming step or startvoltage) at each lesser relevant memory cell age, and less than thevalue of the attribute for at least a subset of lesser memory cell ages.Decreasing functions described herein might, for example, be determinedexperimentally, empirically or through simulation.

Note that the decreasing functions may define attribute values for whichthe memory device is not configured to attain. This may be the result ofconfiguration constraints, e.g., the memory device (e.g., controller ofthe memory device) might be configured to generate some limited numberof different values for the attribute. For example, process variationamong integrated circuit devices is to be expected, and memory devicemanufacturers often provide an ability at the time of fabrication toselect values of such attributes as read voltages, program voltages,erase voltages, etc. to provide the expected performance of the memorydevice despite this process variation. This is often enabled by the useof trim registers, where different values of a trim register correspondto different values of an attribute. After testing of the memory device,these trim registers are set to select the desired attribute value foroperation of the memory device. Typically, these trim registers containone or more digits of storage (e.g., fuses, anti-fuses, memory cells,etc.), and each digital value of a trim register corresponds to aparticular respective attribute value. A one-digit trim register canrepresent one of two attribute values, a two-digit trim register canrepresent one of up to four attribute values, a three-digit trimregister can represent one of up to eight attribute values, etc.

Where a reprogrammable trim register (e.g., using memory cells) is used,the controller (e.g., the internal controller) of the memory devicecould set a register value to vary an attribute value for individualprogramming operations responsive to indications of memory cell age.Table 3 extends the example of Table 2 to show how trim registers mightbe used to select attribute values for the programming operation as afunction of the indications of memory cell age using a two-digit trimregister, while Table 4 extends the example of Table 3 to show how trimregisters might be used to select attribute values for the programmingoperation as a function of the calculated attribute value using atwo-digit trim register. Note that while Table 4 depicts the selectedattribute value as a function of the calculated attribute value, itremains a function of the memory cell age as the calculated attributevalue is a function of the memory cell age.

TABLE 3 Register Values and Attribute Values (Y) as Function of MemoryCell Age (A) Memory Cell Age (A) Register Value Attribute Value (Y) A1<= A < A2 00 Y1 A2 <= A < A3 01 Y2 A3 <= A < A4 10 Y3 A4 <= A <= A5 11Y4

TABLE 4 Register Values and Attribute Values (Y) as Function ofCalculated Attribute Value (Y′) Calculated Attribute Value (Y′) RegisterValue Attribute Value (Y) Y′1 <= Y′ < Y′2 00 Y1 Y′2 <= Y′ < Y′3 01 Y2Y′3 <= Y′ < Y′4 10 Y3 Y′4 <= Y′ <= Y′5 11 Y4

FIG. 10 is a flowchart of a method of configuring a memory in accordancewith an embodiment. At 1001, a read window budget as a function ofprogramming step voltage might be characterized for a plurality ofmemory cell ages. The characterization could be determinedexperimentally, empirically or through simulation. The characterizationmight be a decreasing function for each memory cell age of the pluralityof memory cell ages. Memory cell age might be indicated as a number ofprogram/erase cycles experienced by memory cells being programmed.

At 1003, a respective programming step voltage for each memory cell ageof the plurality of memory cell ages might be determined in response toa desired read window budget. The desired read window budget might bedetermined in response to a capability of an error correction schemeselected for operation of a memory. The desired read window budget mightbe determined to be greater than a minimum read window budget for whichthe selected error correction scheme is capable of correcting expectederrors at a particular (e.g., desired maximum) data age. For example, ifthe error correction scheme is expected to correct X digits of erroneousdata, the desired read window budget might be determined to be a readwindow budget that would be expected to generate some number of digitsof erroneous data that is less than or equal to X as a result oftime-dependent charge loss when the data reaches the particular dataage.

At 1005, data indicative of the determined respective programming stepvoltage for each memory cell age of the plurality of memory cell agesmight be stored to the memory. For example, data for a look-up tablemight be stored to the memory, or data corresponding to constants of anequation might be stored to the memory. A controller (e.g., controllogic 116) of the memory might be configured to perform programmingoperations using the data indicative of the determined respectiveprogramming step voltage for each memory cell age of the plurality ofmemory cell ages.

FIG. 11 is a flowchart of a method of operating a memory in accordancewith an embodiment. At 1111, a memory cell age of a plurality of memorycells might be determined. Determining the memory cell age might includedetermining a number of program/erase cycles experienced by theplurality of memory cells. It is noted that blocks of memory cells areoften erased together. As such, a number of erase operations performedon a block of memory cells might be deemed to correspond to a number ofprogram/erase cycles experienced by any memory cell of that block ofmemory cells. In addition, a predetermined storage location of the blockof memory cells, e.g., a particular number of memory cells of aparticular physical row of memory cells of the block of memory cells,might store an indication of the number of erase operations performed onthe block of memory cells. Accordingly, reading the predeterminedstorage location of the block of memory cells might be used to determinethe memory cell age of a plurality of memory cells of that block ofmemory cells. Other indicators of memory cell age might be used in thealternative. For example, determining a VgVt of a memory cell couldindicate a memory cell age, such as depicted in FIG. 8B.

At 1113, a desired programming step voltage for programming memory cellshaving the determined memory cell age might be determined. This mightinclude calculating a programming step voltage using an equation, orusing a look-up table. At 1115, a programming operation might beperformed on the plurality of memory cells. The programming operationmight apply a plurality of programming pulses to control gates of theplurality of memory cells. A particular programming pulse of theplurality of programming pulses might have a voltage level that is thedesired programming step voltage higher than a voltage level of animmediately prior programming pulse of the plurality of programmingpulses.

FIG. 12 is a flowchart of a method of operating a memory in accordancewith another embodiment. At 1221, a first plurality of programmingpulses might be applied to control gates of a plurality of memory cellsduring a particular programming operation for programming the pluralityof memory cells to respective desired data states of a plurality of datastates. The first plurality of programming pulses might have aparticular slope. For example, a difference in voltage level between aparticular programming pulse of the first plurality of programmingpulses and a prior (e.g., immediately prior) programming pulse of thefirst plurality of programming pulses might have a particular value, anda difference in voltage level between a subsequent (e.g., immediatelysubsequent) programming pulse of the first plurality of programmingpulses and the particular programming pulse of the first plurality ofprogramming pulses might have the particular value. For someembodiments, a difference in voltage level between a subsequent (e.g.,immediately subsequent) programming pulse of the first plurality ofprogramming pulses and any programming pulse of the first plurality ofprogramming pulses might have the particular value. The particular slopemight correspond to a memory cell age of the plurality of memory cellsprior to performing the particular programming operation.

At 1223, a second plurality of programming pulses might be applied tothe control gates of the plurality of memory cells during a subsequentprogramming operation (e.g., subsequent to the particular programmingoperation) for programming the plurality of memory cells to respectivedesired data states of the plurality of data states. The secondplurality of programming pulses might have a different slope less thanthe particular slope. For example, a difference in voltage level betweena particular programming pulse of the second plurality of programmingpulses and a prior (e.g., immediately prior) programming pulse of thesecond plurality of programming pulses might have a different value,less than the particular value, and a difference in voltage levelbetween a subsequent (e.g., immediately subsequent) programming pulse ofthe second plurality of programming pulses and the particularprogramming pulse of the second plurality of programming pulses mighthave the different value. For some embodiments, a difference in voltagelevel between a subsequent (e.g., immediately subsequent) programmingpulse of the second plurality of programming pulses and any programmingpulse of the second plurality of programming pulses might have thedifferent value. The particular slope might correspond to a memory cellage of the plurality of memory cells prior to performing the subsequentprogramming operation.

The method of FIG. 12 might be continued for one or more additionalprogramming operations. For example, at 1225, a third plurality ofprogramming pulses might be applied to the control gates of theplurality of memory cells during a further subsequent programmingoperation (e.g., subsequent to the subsequent programming operation) forprogramming the plurality of memory cells to respective desired datastates of the plurality of data states. The third plurality ofprogramming pulses might have a third slope less than the differentslope. For example, a difference in voltage level between a particularprogramming pulse of the third plurality of programming pulses and aprior (e.g., immediately prior) programming pulse of the third pluralityof programming pulses might have a third value, less than the differentvalue, and a difference in voltage level between a subsequent (e.g.,immediately subsequent) programming pulse of the third plurality ofprogramming pulses and the particular programming pulse of the thirdplurality of programming pulses might have the third value. For someembodiments, a difference in voltage level between a subsequent (e.g.,immediately subsequent) programming pulse of the third plurality ofprogramming pulses and any programming pulse of the third plurality ofprogramming pulses might have the third value. The particular slopemight correspond to a memory cell age of the plurality of memory cellsprior to performing the next subsequent programming operation.

In the method of FIG. 12, one or more intervening programming operationsmight be performed between the particular programming operation of theplurality of memory cells and the subsequent programming operation ofthe plurality of memory cells. In addition, one or more of theintervening programming operations might apply respective pluralities ofprogramming pulses having the particular slope, having the differentslope, or having a respective slope less than the particular slope andgreater than the different slope. Furthermore, one or more interveningprogramming operations might be performed between the subsequentprogramming operation of the plurality of memory cells and the furthersubsequent programming operation of the plurality of memory cells, andone or more of these intervening programming operations might applyrespective pluralities of programming pulses having the different slope,having the third slope, or having a respective slope less than thedifferent slope and greater than the third slope.

Conclusion

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe embodiments will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the embodiments.

What is claimed is:
 1. A method of operating a memory, comprising:determining a memory cell age of a plurality of memory cells;determining a desired programming step voltage for programming memorycells having the determined memory cell age; and performing aprogramming operation on the plurality of memory cells comprisingapplying a plurality of programming pulses to control gates of theplurality of memory cells; wherein a particular programming pulse of theplurality of programming pulses has a voltage level that is the desiredprogramming step voltage higher than a voltage level of an immediatelyprior programming pulse of the plurality of programming pulses.
 2. Themethod of claim 1, wherein determining the memory cell age of theplurality of memory cells for performing the particular programmingoperation comprises determining a number of program/erase cyclesexperienced by the plurality of memory cells prior to performing theparticular programming operation.
 3. The method of claim 1, comprisesdetermining the desired programming step voltage for programming memorycells having the determined memory cell age using a decreasing functionof memory cell age.
 4. The method of claim 3, wherein using thedecreasing function of memory cell age comprises using a steppeddecreasing function of memory cell age.
 5. The method of claim 3,wherein using the decreasing function of memory cell age comprises usinga decreasing function of memory cell age where a value of the desiredprogramming step voltage at a particular memory cell age is less than orequal to a value of the desired programming step voltage at each memorycell age less than the particular memory cell age, and less than thevalue of the desired programming step voltage for at least a subset ofmemory cell ages less than the particular memory cell age.
 6. The methodof claim 1, wherein the desired programming step voltage is a firstdesired programming step voltage, wherein the plurality of programmingpulses is a first plurality of programming pulses, and whereinperforming the programming operation on the plurality of memory cellsfurther comprises: determining a second desired programming step voltagefor programming the plurality of memory cells; and applying a secondplurality of programming pulses to the control gates of the plurality ofmemory cells after applying the first plurality of programming pulses tothe control gates of the plurality of memory cells; wherein the seconddesired programming step voltage is different than the first desiredprogramming step voltage; and wherein a particular programming pulse ofthe second plurality of programming pulses has a voltage level that isthe second desired programming step voltage higher than a voltage levelof an immediately prior programming pulse of the second plurality ofprogramming pulses.
 7. The method of claim 6, wherein the second desiredprogramming step voltage is less than the first desired programming stepvoltage.
 8. The method of claim 6, wherein determining the seconddesired programming step voltage for programming the plurality of memorycells comprises determining the second desired programming step voltagein response to the determined memory cell age.
 9. The method of claim 1,wherein the desired programming step voltage is a second desiredprogramming step voltage, wherein the plurality of programming pulses isa second plurality of programming pulses, and wherein performing theprogramming operation on the plurality of memory cells furthercomprises: determining a first desired programming step voltage forprogramming the plurality of memory cells; and applying a firstplurality of programming pulses to the control gates of the plurality ofmemory cells before applying the second plurality of programming pulsesto the control gates of the plurality of memory cells; wherein the firstdesired programming step voltage is different than the second desiredprogramming step voltage; and wherein a particular programming pulse ofthe first plurality of programming pulses has a voltage level that isthe first desired programming step voltage higher than a voltage levelof an immediately prior programming pulse of the first plurality ofprogramming pulses.
 10. A method of configuring a memory, comprising:characterizing a read window budget for a programming operation of thememory as a function of a programming step voltage for a plurality ofmemory cell ages; determining a respective programming step voltage foreach memory cell age of the plurality of memory cell ages in response toa desired read window budget; and storing data to the memory indicativeof the determined respective programming step voltage for each memorycell age of the plurality of memory cell ages.
 11. The method of claim10, further comprising: selecting an error correction scheme for thememory, wherein the selected error correction scheme has a capability ofcorrecting a particular number of erroneous digits of data stored to aplurality of memory cells by the programming operation; determining avalue of the read window budget that would be expected to generate theparticular number of erroneous digits of data; and selecting the desiredread window budget to have a value greater than or equal to the value ofthe read window budget that would be expected to generate the particularnumber of erroneous digits of data.
 12. The method of claim 10, whereinstoring the data to the memory indicative of the determined respectiveprogramming step voltage for each memory cell age of the plurality ofmemory cell ages comprises storing the data as a look-up table.
 13. Amemory, comprising: an array of memory cells; a trim register storingdata indicative of a respective programming step voltage for aprogramming operation for each memory cell age of a plurality of memorycell ages; and a controller configured to access the array of memorycells; wherein the controller is further configured to: determine amemory cell age of a plurality of memory cells of the array of memorycells; determine a particular respective programming step voltage forthe programming operation corresponding to the determined memory cellage using the stored data indicative of the respective programming stepvoltage for the programming operation for each memory cell age of theplurality of memory cell ages; and perform the programming operation onthe plurality of memory cells using the particular respectiveprogramming step voltage corresponding to the determined memory cellage.
 14. The memory of claim 13, wherein the controller being configuredto perform the programming operation comprises the controller beingconfigured to: apply a plurality of programming pulses to control gatesof the plurality of memory cells; wherein a particular programming pulseof the plurality of programming pulses has a voltage level that is theparticular respective programming step voltage higher than a voltagelevel of an immediately prior programming pulse of the plurality ofprogramming pulses.
 15. The memory of claim 13, wherein the controllerbeing configured to determine the memory cell age of the plurality ofmemory cells comprises the controller being configured to determine anumber of program/erase cycles experienced by the plurality of memorycells prior to performing the programming operation.
 16. The memory ofclaim 13, wherein the controller is further configured to determine theparticular respective programming step voltage using a decreasingfunction of memory cell age.
 17. The memory of claim 16, wherein thecontroller being configured to use the decreasing function of memorycell age comprises the controller being configured to use a steppeddecreasing function of memory cell age.
 18. The memory of claim 16,wherein a value of the particular respective programming step voltage ata particular memory cell age is less than or equal to a value of theparticular respective programming step voltage at each memory cell ageless than the particular memory cell age, and less than the value of theparticular respective programming step voltage for at least a subset ofmemory cell ages less than the particular memory cell age.
 19. Thememory of claim 13, wherein the controller is further configured to:determine a second programming step voltage for the programmingoperation different than the particular respective programming stepvoltage; and perform the programming operation on the plurality ofmemory cells using the particular respective programming step voltagecorresponding to the determined memory cell age for a first plurality ofprogramming pulses applied to control gates of the plurality of memorycells, and further using the second programming step voltage for asecond plurality of programming pulses applied to the control gates ofthe plurality of memory cells after applying the first plurality ofprogramming pulses to the control gates of the plurality of memorycells.
 20. The memory of claim 13, wherein the controller is furtherconfigured to: determine a second programming step voltage for theprogramming operation different than the particular respectiveprogramming step voltage; and perform the programming operation on theplurality of memory cells using the particular respective programmingstep voltage corresponding to the determined memory cell age for a firstplurality of programming pulses applied to control gates of theplurality of memory cells, and further using the second programming stepvoltage for a second plurality of programming pulses applied to thecontrol gates of the plurality of memory cells prior to applying thefirst plurality of programming pulses to the control gates of theplurality of memory cells.